Hardware System Architect Lead, GPU Platform

About Think We make the world's compute radically more efficient. Think AI was founded in Riyadh in 2025 on one problem: expensive silicon sitting underused, held back by software blind to the hardware it runs on. We design and build the machine and the orchestration together, in one building, so that stops being true. Our Mission To redefine AI infrastructure from the silicon up. To build the most efficient compute platform on earth, where hardware and software co-evolve to maximise intelligence. To ignite a new golden age of engineering, where anyone can own, operate, and scale frontier AI without compromise, without dependency, and without wasted compute. Our Values Four principles run through everything we do. We look for these in how people demonstrate the values in their everyday work, not in how they talk about themselves. Ownership مسؤولية You own the outcome, not just the task. You're frugal with resources and you put the mission ahead of your own comfort. Agility مرونة You move with velocity. You ship quickly and reiterate and once a decision is made, you disagree and commit. Impact أثر You build for the customer. You think big and execute simply and you measure yourself on outcomes, not activity. Mastery إتقان You go deep on the hard problem. Excellence is your default and you take real pride in delighting the customer. The Role This role owns the architecture of Think AI's multi-accelerator server platforms, the systems that sit underneath every node SKU in our product line and the ILM orchestration platform that runs on them. The first platform you will own is a high-density multi-accelerator system with true one-to-one GPU-to-NIC affinity that scales in accelerator count rather than stopping at a fixed number, built for a mixed-silicon fabric that runs NVIDIA, AMD, and Intel accelerators side by side. You will take it from block diagram to manufacturing release in our Riyadh facility, and then set the platform direction for every node generation that follows. Today we own the specification and work with a JDM partner on detailed board design; over time this role builds the in-house board design team that brings schematics and layout fully under our control. We want someone who has shipped dense multi-GPU platforms, argued over lane budgets and switch partitioning, and brought a system through EVT, DVT, and PVT into volume. You also own platform quality: nothing leaves the Riyadh floor until it has been validated at board, server and rack level. What You'll Do • Own the system architecture end to end: CPU platform selection, PCIe Gen5 and Gen6 topology, switch selection and partitioning, lane budgets, and GPU-to-NIC affinity across the full chassis. • Design for GPUDirect RDMA and peer-to-peer traffic across heterogeneous accelerators, and validate ACS, ATS, IOMMU, and P2P behavior for each silicon vendor on the platform. • Own the signal integrity strategy across retimers, MCIO and cabled PCIe, risers, backplanes, and channel loss budgets, working with layout and SI engineers through every board spin. • Lead power and thermal architecture for dense, high-TDP accelerator configurations, covering CRPS power delivery, airflow, and liquid-cooling readiness, together with our mechanical and thermal engineers. • Define BIOS/UEFI and BMC requirements, and work with the ILM software team on bring-up, telemetry, firmware, and fabric integration so the hardware and orchestration layers are designed as one system. • Write the platform specification and reference design our JDM partner builds to, and own design reviews of every schematic, layout, and BOM before release. • Select and manage ODM and JDM partners for motherboards, chassis, and PCIe switches, and drive each platform through EVT, DVT, and PVT into production at our Riyadh manufacturing facility. • Lead the move from JDM to in-house board design, taking ownership of schematics, layout, and SI/PI one platform at a time while PCB fabrication and assembly stay with partners, and own the roadmap for future generations, including Gen6 switching, CXL, and rack-scale integration. • Own the platform validation and quality strategy: validation plans, qualification matrices, and EVT, DVT, and PVT entry and exit criteria, covering PCIe link training and margining, memory qualification across DIMM vendors, accelerator and NIC interoperability, thermal, power, and long-duration stress testing. • Drive Design for Test and Manufacturing (DFx) with our manufacturing team so every node can be tested at board, server, and rack level, including factory test coverage, burn-in, and yield targets for production in Riyadh. • Lead failure analysis and root cause for platform issues from first power-on through mass production, working from BIOS, BMC, firmware, and OS logs and lab instrumentation, and own the corrective-action reports and debug guides shared with manufacturing, partners, and customers. • Build validation and test automation in Python and Bash, tied into ILM telemetry, so qualification and factory testing scale with production volume. • Build and lead the hardware platform team over time, starting with board design, SI/PCIe, mechanical/thermal, platform firmware, and platform validation and test. What You Bring • 12+ years in hardware or system architecture, with a focus on GPU-accelerated or accelerator-dense servers, at an accelerator vendor, server OEM, or ODM or a hyperscaler hardware team. • Has shipped at least one dense multi-GPU server platform from architecture through PVT and into production. • Deep PCIe expertise: switch topologies, Gen5 and Gen6 signal integrity, retimers, enumeration, and BAR and resource allocation at scale. • Strong working knowledge of RDMA NICs, GPUDirect, NUMA, IOMMU, and GPU-to-NIC communication, plus power delivery and thermal constraints in dense form factors. • Comfortable reading schematics, leading layout reviews, and debugging in the lab with a scope and a PCIe protocol analyzer. • Hands-on platform bring-up, validation, and failure analysis from first power-on through production ramp, including factory debug at ODM or manufacturing sites. • Experience writing validation plans and qualification matrices, and driving root cause and corrective action through to closure, with Python and Bash for test automation. • Fluent English. Nice to Have • Hands-on schematic design for server motherboards, risers, or PCIe switch and retimer boards. • Experience across more than one accelerator vendor on the same platform. • Open interconnect standards such as UALink for scale-up and Ultra Ethernet (UEC) for scale-out, alongside NVLink-class and CXL experience. • HGX, OAM, or UBB baseboards, OCP or ORv3 rack integration, and liquid-cooled server design. • DDR5 qualification and margin analysis across multiple DIMM vendors. • Rack-level (L10 to L11) integration and test, or reliability testing such as HALT and HASS. • Prior experience inside a startup scaling from early to growth stage. What we offer • One of the first deep tech companies in the region, building foundational technology in house. • Meaningful ownership and impact at an early stage. • Competitive early-stage compensation. • Close collaboration with a small, senior team. • Problems that combine hardware, systems and AI at scale. Show more Show less